Silogy
Silogy’s Viv AI verification engineer helps chip developers root-cause test failures faster by automating debugging with log files, code, and waveforms. Boost your team’s productivity with on-premise, secure AI that works around the clock.
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Key features of Silogy
- AI root-cause analysis Analyzes code, logs, waveforms and specs to find the root cause of a failing test and produce a detailed bug report, typically in minutes.
- Waveform analysis Queries multi-gigabyte waveform files (FST, VCD, FSDB) directly, so you don't have to manually inspect waveforms.
- Swarm investigation Spawns 3-5 investigator agents per failure hypothesis and merges their reports into a unified bug description.
- On-premise execution Runs entirely within your infrastructure; no design data ever leaves your data centers.
- CI/CD headless mode Runs headless when stdin is not a TTY, outputting a Markdown bug report to stdout for CI pipelines.
Verified Oct 31, 2026 · Source
Who Silogy is for
Chip developers and verification engineers who need to root-cause failing simulation tests faster.
Teams with no failing test case to start from, since Viv's analysis always begins with one.
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Silogy FAQ
Does any data leave my data center?
No. Viv runs entirely on-premise. Your code, logs, waveforms, and specifications stay within your infrastructure. The only external communication is with the LLM API provider you configure.
What LLM providers can I use?
Viv works with OpenAI, Claude (Anthropic), Llama, and any vLLM-compatible endpoint. You bring your own API key.
Can I use Viv in CI/CD pipelines?
Yes. Viv automatically runs in headless mode when stdin is not a TTY, outputting a Markdown bug report to stdout.
What waveform formats does Viv support?
Viv supports FST, VCD, and FSDB waveform files.
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